1. Technical Field
The invention relates generally to testing of integrated circuits, and more specifically to built-in-self-test (BIST) circuits and methods implementable on an integrated circuit chip for testing the integrated circuit having a multi-ported memory array.
2. Related Art
Advances in computer technology have led to a development of multi-processor computers having multi-ported memory devices. Such memory devices can have fault modes, such as typical cell faults (e.g., stuck-at, transition, coupling, etc.) which must be tested for and detected early in the production process before the memory devices are installed, since the faults can cause the failure of the computers or other electronic structures that the memory devices are intended to be used with.
The testing of memory may be performed by an external tester, such as a piece of automatic test equipment (ATE), or may be performed internally in the memory device. Internal testing is referred to as built-in self-test (BIST), which may be used in conjunction with deterministic test algorithms. The most popular and widely accepted deterministic test algorithm is known as a MARCH algorithm. BIST algorithms include a MARCH algorithm. See A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons Ltd., England, 1991; B. Nadeau-Dostie, A. Silburt and V. K. Agarwal, “Serial Interfacing for Embedded Memory Testing,” IEEE Design and Test of Computers, April 1990, p. 52.
The types of tests required for a large multiported memory are quite complex, and may vary depending upon external parameters such as temperature and operating voltage, and therefore a flexible BIST is required. The flexible nature of the BIST disclosed in U.S. Pat. No. 5,961,653, issued to Kalter, et al., and assigned to International Business Machines Corp., aids in the implementation of some single-port access tests.
Previously, multiport memory BISTs have been designed for single-ported memory structures and multi-ported memories using finite state machines (FSM) to implement memory testing algorithms. See FIG. 1a and FIG. 1b. An FSM executes a predetermined set of patterns (e.g., write and read operations) with little or no flexibility. A typical FSM BIST is custom designed for a given memory and a predefined set of tests. Any new test for a memory requires a new FSM BIST design, which may require a redesign of the entire integrated circuit.
In a typical memory BIST employing a finite state machine (FSM) such as the FSM BIST 111 in FIG. 1a and the FSM BIST 112 in FIG. 1b, the data patterns, address sequencing, and control sequence that will be run for every test are fixed in the BIST logic implemented in hardware. This technique is generally inadequate for testing DRAMs because of the inflexibility of the BIST logic to cover the data pattern, address sequencing, and control sensitivities which can be process or parametric dependent and which can change with time (e.g., after manufacture of the integrated circuit).
There is a need for a programable BIST circuit that will perform robust testing of multiported memories, including a need for a BIST having a high degree of flexibility in address sequencing, data patterns, and control signals for effectively testing multiported memories. Additionally, there is a need for an optimally effective and economical BIST circuit to detect faulty designs and units early in the production process, or whenever, (e.g., during or after production), a new fault mode is discovered.